ok6410的Nand Flash驱动

2530阅读　0评论2013-09-11　archer239915
分类：嵌入式

1. Linux的MTD系统：
    在linux的用户空间中访问flash时要经过三层，
   一是上层设备层，核心导出字符设备和块设备；字符设备定义在mtdchar.c（major为90），实现了file_operations，都是调用下层的函数。
   块设备定义了mtdblk_dev，每个块设备对应一个分区，即mtd_part（major为31）。
   二是中间层原始设备层，用mtd_part表示分区，对应上层的每个次设备号，mtd_info表示一个芯片设备描述，上层的读写函数会
    通过核心调用这个结构的相关函数。可以用add_mtd_partitions向核心添加几个新的分区（用mtd_part表示），这需要描述分区
    信息的结构mtd_partition（在板文件定义）和整个芯片属性和方法的结构mtd_info（这里面包含了读写和控制函数，会调用下层的函数）。
   三是底层芯片级驱动，主要是nand_chip结构体，mtd_info的priv指针指向nand_chip，所以中间层的函数通过这个指针调用nand_chip中的
   函数。这个结构体包含了关于nand flash的地址信息，读写方法，ECC模式，硬件控制等一系列底层机制。我们只需要定义nand_chip的
    这些成员，因为内核的nand_base.c实现了很多通用代码。

    我们要做的就是第三步，先实现nand_chip的有关成员，这与硬件有关，再用nand_scan（mtd_info *mtd ），这会探测芯片，
    探测芯片即调用nand_chip中的函数并用nand_chip的成员初始化mtd_info，这是整个芯片的中间层描述，再调用add_mtd_partitions，
    即用板文件的分区表mtd_partition数组和前面准备的mtd_info向核心添加整个芯片的所有分区，即是新建几个mtd_part,每个表示一个
    分区，这里面包含mtd_info，其中大多成员直接指向整个芯片的mtd_info，因为分区的操作与芯片的操作是一样的。

2. 实现ok6410的nand flash驱动：
    首先在板文件定义struct mtd_partition ok6410_nand_part[]，即分区信息，struct s3c2410_nand_set ok6410_nand_sets[]
     即所有芯片信息，这里就只有一个芯片；struct s3c2410_platform_nand ok6410_nand_info，包含前面信息和芯片属性的
     platform_data;最后用s3c_nand_set_platdata(&ok6410_nand_info);形成platform_device,注册到platform总线。
     总线会由name找到（match）驱动，即在s3c-nand.c，执行驱动的probe。下面是这个函数：
    主要流程为：
    a. 得到clk并打开时钟
    b. 申请I/O内存并映射到内核虚拟地址
    c. 申请nand_chip和mtd_info的内存，根据电路板情况初始化nand_chip的成员
    d. 将mtd_info的priv指向nand_chip（下面调用的函数都是nand_chip中的）
    e. nand_scan探测nand_flash,这时会读取芯片ID，并用nand_chip初始化mtd_info
    f. 调用mtd_add_partitions，用板文件的分区表mtd_partition和上面芯片的mtd_info，新建分区，即几个mtd_part
    g. 以后MTD上层访问某个分区，都可以由mtd_part的mtd_info找到nand_flash，并调用其中的函数

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  1. /* s3c_nand_probe
  2.  *
  3.  * called by device layer when it finds a device matching
  4.  * one our driver can handled. This code checks to see if
  5.  * it can allocate all necessary resources then calls the
  6.  * nand layer to look for devices
  7.  */
  8. static int s3c_nand_probe(struct platform_device *pdev, enum s3c_cpu_type cpu_type)
  9. {    
  10.     struct s3c2410_platform_nand *plat = pdev->dev.platform_data;
  11.     struct s3c2410_nand_set *sets;
  12.     struct nand_chip *nand;
  13.     struct resource *res;
  14.     int err = 0;
  15.     int ret = 0;
  16.     int nr_sets;
  17.     int i, j, size;

  19. #if defined(CONFIG_MTD_NAND_S3C_HWECC)
  20.     struct nand_flash_dev *type = NULL;
  21.     u_char tmp;
  22.     u_char dev_id;
  23. #endif

  25.     /* get the clock source and enable it */

  27.     s3c_nand.clk = clk_get(&pdev->dev, "nand");
  28.     if (IS_ERR(s3c_nand.clk)) {
  29.         dev_err(&pdev->dev, "failed to get clock");
  30.         err = -ENOENT;
  31.         goto exit_error;
  32.     }

  34.     clk_enable(s3c_nand.clk);

  36.     /* allocate and map the resource */

  38.     /* currently we assume we have the one resource */
  39.     res = pdev->resource;
  40.     size = res->end - res->start + 1;

  42.     s3c_nand.area = request_mem_region(res->start, size, pdev->name);

  44.     if (s3c_nand.area == NULL) {
  45.         dev_err(&pdev->dev, "cannot reserve register region\n");
  46.         err = -ENOENT;
  47.         goto exit_error;
  48.     }

  50.     s3c_nand.cpu_type = cpu_type;
  51.     s3c_nand.device = &pdev->dev;
  52.     s3c_nand.regs = ioremap(res->start, size);
  53.     s3c_nand.platform = plat;

  55.     if (s3c_nand.regs == NULL) {
  56.         dev_err(&pdev->dev, "cannot reserve register region\n");
  57.         err = -EIO;
  58.         goto exit_error;
  59.     }
  60.     sets = (plat != NULL) ? plat->sets : NULL;
  61.     nr_sets = (plat != NULL) ? plat->nr_sets : 1;

  63.     s3c_nand.mtd_count = nr_sets;

  65.     /* allocate memory for MTD device structure and private data */
  66.     s3c_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);

  68.     if (!s3c_mtd) {
  69.         printk("Unable to allocate NAND MTD dev structure.\n");
  70.         return -ENOMEM;
  71.     }

  73.     /* Get pointer to private data */
  74.     nand = (struct nand_chip *) (&s3c_mtd[1]);

  76.     /* Initialize structures */
  77.     memset((char *) s3c_mtd, 0, sizeof(struct mtd_info));
  78.     memset((char *) nand, 0, sizeof(struct nand_chip));

  80.     /* Link the private data with the MTD structure */
  81.     s3c_mtd->priv = nand;



  85.     for (i = 0; i < sets->nr_chips; i++)
  86.     {
  87.         nand->IO_ADDR_R        = (char *)(s3c_nand.regs + S3C_NFDATA);
  88.         nand->IO_ADDR_W        = (char *)(s3c_nand.regs + S3C_NFDATA);
  89.         nand->cmd_ctrl        = s3c_nand_hwcontrol;
  90.         nand->dev_ready        = s3c_nand_device_ready;
  91.         nand->scan_bbt        = s3c_nand_scan_bbt;
  92.         nand->options        = 0;

  94. #if defined(CONFIG_MTD_NAND_S3C_CACHEDPROG)
  95.         nand->options        |= NAND_CACHEPRG;
  96. #endif

  98. #if defined(CONFIG_MTD_NAND_S3C_HWECC)
  99.         nand->ecc.mode        = NAND_ECC_HW;
  100.         nand->ecc.hwctl        = s3c_nand_enable_hwecc;
  101.         nand->ecc.calculate    = s3c_nand_calculate_ecc;
  102.         nand->ecc.correct    = s3c_nand_correct_data;


  105.         // K9GAG08U0E must add below codes
  106.         {
  107.             s3c_nand_hwcontrol(0, NAND_CMD_RESET, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  108.             s3c_nand_device_wait_ready(0);

  110.         }

  112.         s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  113.         s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
  114.         s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE);
  115.         s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  116.         //s3c_nand_device_ready(0);

  118.         s3c_nand_device_wait_ready(0);

  120.          u32 manuf=tmp = readb(nand->IO_ADDR_R); /* Maf. ID */
  121.        

  123.         dev_id = tmp = readb(nand->IO_ADDR_R); /* Device ID */

  125.         printk("forlinx nandflash dev_id=%x\n",dev_id);

  127.         for (j = 0; nand_flash_ids[j].name != NULL; j++) {
  128.             if (tmp == nand_flash_ids[j].id) {
  129.                 type = &nand_flash_ids[j];
  130.                 break;
  131.             }
  132.         }

  134.         if (!type) {
  135.             printk("Unknown NAND Device.\n");
  136.             goto exit_error;
  137.         }

  139.         nand->cellinfo = readb(nand->IO_ADDR_R);    /* the 3rd byte */
  140.         tmp = readb(nand->IO_ADDR_R);            /* the 4th byte */
  141.         if (!type->pagesize)
  142.         {
  143.             if (((nand->cellinfo >> 2) & 0x3) == 0)
  144.             {

  146.                 nand_type = S3C_NAND_TYPE_SLC;
  147.                 nand->ecc.size = 512;
  148.                 nand->ecc.bytes    = 4;

  150.                 if ((1024 << (tmp & 0x3)) > 512)
  151.                 {
  152.                     nand->ecc.read_page = s3c_nand_read_page_1bit;
  153.                     nand->ecc.write_page = s3c_nand_write_page_1bit;
  154.                     nand->ecc.read_oob = s3c_nand_read_oob_1bit;
  155.                     nand->ecc.write_oob = s3c_nand_write_oob_1bit;
  156.                     nand->ecc.layout = &s3c_nand_oob_64;

  158.                     printk("forlinx********Nandflash:Type=SLC ChipName:samsung-K9F2G08U0B or hynix-HY27UF082G2B****** \n");


  161.                 } else
  162.                 {
  163.                     nand->ecc.layout = &s3c_nand_oob_16;
  164.                 }

  166.             } else
  167.             {
  168.                 // int childType=tmp & 0x03; //Page size
  169.                 int childType = nand->cellinfo;

  171.                 if(dev_id == 0xd5)
  172.                 {

  174.                     nand_type = S3C_NAND_TYPE_MLC_8BIT;
  175.                     nand->ecc.read_page = s3c_nand_read_page_8bit;
  176.                     nand->ecc.write_page = s3c_nand_write_page_8bit;
  177.                     nand->ecc.size = 512;
  178.                     nand->ecc.bytes = 13;

  180.                     if(childType==0x94)
  181.                     {
  182.                         //K9GAG08U0D size=2GB type=MLC Page=4K
  183.                         nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;
  184.                         printk("forlinx****Nandflash:ChipType= MLC ChipName=samsung-K9GAG08U0D************ \n");
  185.                     }
  186.                     else if(childType==0x14)
  187.                     {
  188.                         //K9GAG08U0M size=2GB type=MLC Page=4K
  189.                         nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;
  190.                         printk("forlinx****Nandflash:ChipType= MLC ChipName=samsung-K9GAG08U0M************ \n");
  191.                     }
  192.                     else if(childType==0x84)
  193.                     {
  194.                         //K9GAG08U0E size=2GB type=MLC Page=8K
  195.                         nand->ecc.layout = &s3c_nand_oob_mlc_232_8bit;
  196.                         printk("forlinx****Nandflash:ChipType= MLC ChipName=samsung-K9GAG08U0E************ \n");

  198.                     }


  201.                 }else if(dev_id == 0xd7)
  202.                 {
  203.                     nand_type = S3C_NAND_TYPE_MLC_8BIT;
  204.                     nand->ecc.read_page = s3c_nand_read_page_8bit;
  205.                     nand->ecc.write_page = s3c_nand_write_page_8bit;
  206.                     nand->ecc.size = 512;
  207.                     nand->ecc.bytes = 13;
  208.                     nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;
  209.                     printk("forlinx****Nandflash:ChipType= MLC ChipName=samsung-K9LBG08U0D************ \n");


  212.                 }
  213.                 else if(dev_id == 0xd3)
  214.                 {
  215.                     nand_type = S3C_NAND_TYPE_MLC_4BIT;
  216.                     nand->options |= NAND_NO_SUBPAGE_WRITE;    /* NOP = 1 if MLC */
  217.                     nand->ecc.read_page = s3c_nand_read_page_4bit;
  218.                     nand->ecc.write_page = s3c_nand_write_page_4bit;
  219.                     nand->ecc.size = 512;
  220.                     nand->ecc.bytes = 8;    /* really 7 bytes */
  221.                     nand->ecc.layout = &s3c_nand_oob_mlc_64;

  223.                     printk("forlinx****Nandflash:ChipType=MLC ChipName=samsung-K9G8G08U0A************** \n");

  225.                 }

  227.             }

  229.         } else if(dev_id == 0xd7)
  230.         {
  231.             nand_type = S3C_NAND_TYPE_MLC_8BIT;
  232.             nand->ecc.read_page = s3c_nand_read_page_8bit;
  233.             nand->ecc.write_page = s3c_nand_write_page_8bit;
  234.             nand->ecc.size = 512;
  235.             nand->ecc.bytes = 13;
  236.             nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;
  237.             printk("forlinx****Nandflash:ChipType= MLC ChipName=samsung-K9LBG08U0D************ \n");

  239.         }
  240.         else if(manuf==0x2c && dev_id ==0x48)
  241.         {
  242.             //MT29F16G08ABACAWP size=2GB type=SLC Page=4K
  243.             nand_type = S3C_NAND_TYPE_MLC_8BIT;
  244.             nand->ecc.read_page = s3c_nand_read_page_8bit;
  245.             nand->ecc.write_page = s3c_nand_write_page_8bit;
  246.             nand->ecc.size = 512;
  247.             nand->ecc.bytes = 13;
  248.             nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;

  250.             printk("forlinx******Nandflash:ChipType= SLC ChipName=MT29F16G08ABACAWP\n");

  252.         } else if(manuf==0x2c && dev_id ==0x38)
  253.         {
  254.                 //MT29F16G08ABACAWP size=1GB type=SLC Page=4K
  255.                 nand_type = S3C_NAND_TYPE_MLC_8BIT;
  256.                 nand->ecc.read_page = s3c_nand_read_page_8bit;
  257.                 nand->ecc.write_page = s3c_nand_write_page_8bit;
  258.                 nand->ecc.size = 512;
  259.                 nand->ecc.bytes = 13;
  260.                 nand->ecc.layout = &s3c_nand_oob_mlc_128_8bit;

  262.                 printk("forlinx******Nandflash:ChipType= SLC ChipName=MT29F8G08ABABAWP\n");

  264.         }else
  265.         {
  266.             nand_type = S3C_NAND_TYPE_SLC;
  267.             nand->ecc.size = 512;
  268.             nand->cellinfo = 0;
  269.             nand->ecc.bytes = 4;
  270.             nand->ecc.layout = &s3c_nand_oob_16;
  271.             printk("forlinx *****Nandflash:ChipType= Unknow\n");

  273.         }

  275.         printk("S3C NAND Driver is using hardware ECC.\n");
  276. #else
  277.         nand->ecc.mode = NAND_ECC_SOFT;
  278.         printk("S3C NAND Driver is using software ECC.\n");
  279. #endif
  280.         if (nand_scan(s3c_mtd, 1)) {
  281.             ret = -ENXIO;
  282.             goto exit_error;
  283.         }

  285.         /* Register the partitions */
  286.         add_mtd_partitions(s3c_mtd, sets->partitions, sets->nr_partitions);
  287.     }

  289.     pr_debug("initialized ok\n");
  290.     return 0;

  292. exit_error:
  293.     kfree(s3c_mtd);


  296.     return ret;
  297. }







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