Maciej W. Rozycki wrote:
>
> There are actually two D-latches between the input and the priority
> resolver. You are clearly writing of the ISR latch which is really reset
> by EOI. But the reason of spurious interrupts is the IRR D-latch which is
> located earlier in the path from IR
> IRR latch normally reflects the IR
> start of the first INTA cycle (it also gets reset by ICW1 but this doesn't
> matter here). But the CPU probes for INT at the late stage of execution
> of an instruction. There is a small window between the INT probe and the
> start of the first INTA cycle. If the IR
> this window and no other IR
> spurious interrupt -- an 8259A issues a default vector which is that of
> IR7.
Exactly!
>From my notes of long ago, Spurious Interrupts occur when:
- Interrupt pin is asserted in level sensitive mode, and the asserted
level is negated before the interrupt is acknowledged.
- Interrupt pin is asserted for an interrupt source that is later
masked using the mask bit in the vector/priority register before
the interrupt is acknowledged.
- Some UARTs can generate spurious interrupts if you clear the IER
(Interrupt Enable Register) right before an interrupt occurs.
Same result, interrupt generated but not present during the
acknowledge cycle.
- There are more, but you get the idea.
This appears to be an desired behavior. I remember that the OpenPIC
interrupt controller (AMD/CYRIX SMP response to the APIC) has the same
(non?) feature...
Bob